1. Field of the Invention
This invention relates to circuitry for digital logic functions, and more particularly to pass gate circuitry for fast exclusive OR and exclusive NOR logic functions.
2. Related Art
Static CMOS digital logic circuitry is very popular because it has low power consumption and it is relatively easy to design however, it typically requires a relatively large number of transistors and the path through static CMOS logic circuitry typically includes numerous transistors in series for even a simple logic function. Pass gate logic circuitry in CMOS circuitry typically requires fewer transistors, resulting in smaller, faster circuits. However, in order to avoid signal degradation, these pass gate logic circuits typically have to be enlarged because each pass gate requires two transistors instead of one, or else output buffers are needed.
Another problem with pass gate logic CMOS circuitry concerns exclusive OR (xe2x80x9cXORxe2x80x9d) and exclusive NOR (xe2x80x9cXNORxe2x80x9d) logic circuitry. (An XOR logic circuit has two or more inputs and a corresponding output which is high if one and only one input is high, and otherwise is low. An XNOR logic circuit has two or more inputs and a corresponding output which is low if one and only one input is high, and otherwise is high.) A problem with XOR and XNOR prior pass gate logic circuitry has been a lack of symmetry in structure, resulting in asymmetrical signal transitions.
U.S. Pat. No. 5,334,880, xe2x80x9cFast Exclusive OR and Exclusive NOR Gates,xe2x80x9d Bodas, uses pass gates for all logic except for the case where both inputs are de asserted. This results in very non-symmetric signal transitions. Also, it has the typical pass gate disadvantage that input signals are transmitted through pass gates to the output and thereby attenuated. Finally, this gate requires four transistors for the logic function plus three more keeper transistors to deal with the signal degradation.
U.S. Pat. No. 5,523,707, xe2x80x9cFast, Low Power Exclusive OR Circuits,xe2x80x9d Levy at al., is pass gates, two keeper transistors and buffering output inverters. Low logic values and high logic values have transmission means of disparate quality. Low voltages get high-quality transmission since the logic devices are NFET""s. High voltages need help from the PFET keeper devices to become full voltages. For some input signal changes, the signal gets transmitted from a transistor""s gate to its drain, but for others it gets transmitted from drain to source, which is a higher resistance path. For example, when the first input rises to a high voltage while the second input is already high, a high-quality xe2x80x9c0xe2x80x9d is transmitted through a transistor channel. But when the second input rises to a high value while the first input is low, a high-quality xe2x80x9c1xe2x80x9d is transmitted from a transistors gate to drain. Thus, signal transitions for this logic circuitry are asymmetrical.
U.S. Pat. No. 5,736,868, xe2x80x9cExclusive Or/Nor Gate Circuit,xe2x80x9d Kim et al., uses pass gates and a NOR gate at the inputs. This logic circuitry also operates asymmetrically. First, inputs are connected to the NFET transistors and a pulldown stack, among other places. Thus, one input is asymmetrically connected to a higher level in the stack than the other input. Secondly, another asymmetry arises because when both inputs are low a NFET transistor connects the output to ground, but when both inputs are high, a two transistors stack connects the output to ground. Furthermore, the typical number of transistors for this logic circuitry function is no smaller than the number of transistors for the present invention.
U.S. Pat. No. 5,861,762, xe2x80x9cInverse Toggle XNOR and XOR Circuit,xe2x80x9d Sutherland, uses four pass gates, but is only efficient for certain applications where there exists a known order of changing input signals. Also, it too produces asymmetrical signal transitions.
Thus a need exists for improved XOR and XNOR logic circuitry.
The foregoing need is addressed in the present invention, according to which circuitry for a XOR or XNOR digital logic function is symmetrically configured, with one level of pass transistors for gating. It is advantageous that the circuitry of the present invention has a symmetrical structure of pass gates so that it provides very fast operation with substantially symmetrical signal transitions. Furthermore it does so using fewer transistors than conventional static CMOS circuitry and provides the same logic function at a comparable or faster speed.
In one aspect, the circuitry includes a first pair of input nodes for receiving respective first and second input signals, a second pair of input nodes for receiving respective complements of the first and second input signals, and an output node. The circuitry has a plurality of PFET-NFET pass gates. Such a pass gate has a first conducting electrode of the pass gate PFET connected to a first conducting electrode of the pass gate NFET, providing a first conducting node of the pass gate, and a second conducting electrode of the pass gate PFET connected to a second conducting electrode of the pass gate NFET, providing a second conducting node of the pass gate. The input nodes are connected to first conducting nodes of respective ones of the plurality of pass gates, and the second conducting nodes of the plurality of pass gates are connected to the circuitry output node.
The circuitry of the present invention is fast because pass gates are inherently fast and because circuitry has a path from input to output with only one transistor in the path for any combination of input signals. This single-transistor path not only contributes to the fast speed of operation for the circuitry, but also reduces attenuation of the input signals which pass through the circuitry to the output. This reduced attenuation is important, since in an embodiment the circuitry receives only input signals and no separate operating power supply. Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.